Personal: “RPU” RISC-V soft CPU core able to run DooM on own SoC implementation to HDMI outut.
Personal: Own FPGA RISC-V CPU “RPU” Listed on official RISV-C core implementation list.
Personal: Started work on my own RISC-V FPGA CPU, “RPU” - continued the “Designing a CPU in VHDL” blog series using this core.
Personal:
Blog series “TeensyZ80” on running a Z80 CPU using a microcontroller emulating the main system board. Touched on hardware considerations, design speccing, low-level development and implemented OS features such as multithreadding.
Started personal blog series “TPU” on Designing a CPU in VHDL. Walks through the implementation of a 16-bit custom CPU named TPU, with associated peripherals such as UART. Featured on Hackaday.
Advised IHV of hardware features required for source level GPU shader debugging, including true jit-compiled on-target expression evaluation.
Delivered source-level debugger based on LLDB for a mobile GPU.
Oversaw delivery of source-level debugger based on LLDB for a DSP.
Speaker at the San Francisco LLVM meeting, discussing bringing new architectures to the LLDB debugger project such as Qualcomms Hexagon DSP.
Patent: Multi-processor code for modification for storage areas - “A method for processing computer program code to enable different parts of the computer program code to be executed by different processing elements of a plurality of communicating processing elements.”
Personal: Blog series “Pi On the Wall” creating a wall-mounted home server with a modified Raspberry Pi board, custom power solution and enclosure. Featured on Hackaday.
Launched own indie racing car game with bespoke online services system.
Developed various aspects of Nascar The Game for PS3 & Xbox 360 including offloading elements to SPU and designing a metal damage system which works on both systems effectively with minimum synchronization points.
Developed and released hetrogeneous debugger for PS3 single source spu/ppu compiler. Included features such as single stepping over architctural barriers from ppu to spu and viewing internal software cache and DMA states.
Head of all videogames related projects.
Contracted for due-dilligence work on the technology foundations of a PS3 title.
Integrated technology into a AAA game engine for PlayStation3.
Created systems for identifying possible data movement bottlnecks and communicating to users at both compile and runtime.
Threading Building Blocks port for PS3 with Automatic SPU offload.
Developed the Offload C++ system for migrating blocks of code in a single-source way to accellerators such as PS3 SPUs.
Developed various optimizations for the Offload C++ system mainly encompassing memory and pointer alignment details being preserved through to the backend as far as possible for late optimization.
Winner of the Elektra 2008 Research and Design award.
Continued C backend work for multiple backend toolchain support, and extending level of C++ high level constructs able to be build via the C backend.
Paper: Strict and Relaxed Sieving for Multi-Core Programming. MULTIPROG’08
Listed as inventor on first patents (granted 2012) on parallel computation.
Developed C backend for VectorC compiler engine.
Development tools and compiler optimizations for the AGEIA PhysX hardware which were used before the technology was acquired by NVIDIA.
Contributor to Multicore Association MCAPI.
Patent filings
Patent: System and method for parallel execution of a program
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