All articles

Designing a RISC-V CPU in VHDL, Part 22: Doom as a benchmark and adding Cache to RPU Jan 9, 2022
Writing the SPI flash of the miniSpartan3 FPGA board Jul 22, 2021
Designing a RISC-V CPU in VHDL, Part 21: Multi-cycle execute for multiply and divide May 29, 2021
Designing a RISC-V CPU in VHDL, Part 20: Interrupts and Exceptions Oct 3, 2020
Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality Feb 13, 2020
Raspberry Pi 4 PCI Express: It actually works! USB3, SATA… GPUs? Aug 30, 2019
Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit Jul 16, 2019
Flashback: Quake 3/RTCW Level Design Feb 11, 2019
Designing a RISC-V CPU in VHDL, Part 17: DDR3 Memory Controller, Clock domain crossing Oct 21, 2018
Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI Sep 26, 2018
Designing a CPU in VHDL, Part 15: Introducing RPU Jun 7, 2018
HDMI over Pmod using the Arty Spartan 7 FPGA board May 5, 2018
The Boat PC – a marine based Raspberry Pi project Aug 13, 2017
Porting my VHDL Character Generator to Spartan3: Reducing clock speeds and pipelining Jul 26, 2016
Designing a CPU in VHDL, Part 14: ISA changes, software interrupts and bugfixing that BIOS code May 29, 2016
Getting Started with the miniSpartan3 FPGA board May 18, 2016
Designing a CPU in VHDL, Part 13: Memory system and BIOS beginnings May 17, 2016
Designing a CPU in VHDL, Part 12: Text mode video output May 7, 2016
Designing a CPU in VHDL, Part 11: VRAM and HDMI output Apr 27, 2016
Dear ImGui, Thanks, From TEMU – The TPU Emulator Mar 31, 2016
Designing a CPU in VHDL, Part 10b: A very irritating issue, resolved. Feb 10, 2016
Designing a CPU in VHDL, Part 10: Interrupts and Xilinx block RAMs Oct 31, 2015
Designing a CPU in VHDL, Part 9: Byte addressing, memory subsystem and UART Sep 30, 2015
A UART Implementation in VHDL Sep 15, 2015
Designing a CPU in VHDL, Part 8: Revisiting the ISA, function calling, assembler Aug 5, 2015
Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA Jul 30, 2015
Designing a CPU in VHDL, Part 6: Program Counter, Instruction Fetch, Branching Jul 23, 2015
Designing a CPU in VHDL, Part 5: Pipeline and Control Unit Jul 18, 2015
Designing a CPU in VHDL, Part 4: The ALU, Comparisons and Branching Jul 14, 2015
Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM Jun 28, 2015
Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, register file, testing Jun 22, 2015
Designing a CPU in VHDL, Part 1: Rationale, tools, method Jun 18, 2015
Teensy Z80 Homebrew Computer – Part 6 – Asynchronous Clocking Fail Feb 16, 2015
Teensy Z80 Homebrew Computer – Part 5 – Implementing preemptive multithreading Feb 1, 2015
Teensy Z80 – Part 4 – VRAM explained, display modes, simple shell. Jan 27, 2015
Teensy Z80 – Part 3 – File System, SD Card, VRAM? Jan 18, 2015
Teensy Z80 – Part 2 – Mode 2 Interrupts, Timer Jan 11, 2015
Teensy Z80 – Part 1 – Intro, Memory, Serial I/O and Display Jan 9, 2015
KiCad – Adding bridges / links to single sided PCB layouts Oct 1, 2014
Pi On The Wall – wall mounted home server – Part 4: Putting it together Sep 29, 2014
Video: PiOnTheWall – Wall Mounted Touchscreen Raspberry Pi Home Server Sep 4, 2014
Video: Windows Developer Program for IoT – Galileo Development Kit Unboxing. Sep 2, 2014
Pi On The Wall – wall mounted home server – Part 3: Reducing Power Consumption Aug 8, 2014
Pi On The Wall – wall mounted home server – Part 2: Diet Pi Jul 11, 2014
Pi On The Wall – wall mounted home server – Part 1: Introduction Jun 27, 2014
Cheap 1.8″ SPI 128×160 TFT Module – Arduino wiring! Jun 10, 2014
Project BoilerLog: SD Datalogger with RTC Mar 9, 2014
Electronics Jan 23, 2014
A change Jan 23, 2014
Gears of Glory: Apex Ace – Singleplayer Game Modes Sep 14, 2012
Gears of Glory: Apex Ace Pricing Aug 26, 2012
Lessons from exhibiting at an Indie Festival Aug 20, 2012
Gears of Glory: Apex Ace status update Jul 23, 2012
Press Release: Gears of Glory: Apex Ace announced. Mar 20, 2012
Leaderboard Ordering Mar 1, 2012