2024
Senior Manager Software Development, Core Technology Group, AMD
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- Presented “High Performance Rendering in Snowdrop Using AMD FidelityFX™ Super Resolution 3 (FSR 3)” At GDC 24 in San Francisco alongside Hampus Siversson from Massive Entertainment.
- Announced FSR 3.1 at Game Developers Conference.
2023
Senior Manager Software Development, Core Technology Group, AMD
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- Promoted to Senior Manager and given Core Technology Group (CTG) management remit - the team who release FidelityFX technologies for desktop and other ecosystems.
- Core member of the FidelityFX Super Resolution 3.0 team. Released 3.0.
- Released FSR 2.2.
- CEDEC 2023 awards nominee - FidelityFX SDK - excellence in engineering.
2022
Manager Software Development, Core Technology Group, AMD
- Core member of the FidelityFX Super Resolution 2.0 team. Released 2.0 and 2.1.
- FSR 2.0 announcement presentation for GDC.
- Further expanded upon “Fidelity on Xbox” strategy with dual PC/Console release roadmap.
- Strategy decisions made in 2021 come to fruition with multiple console titles shipping with CTG technologies.
- Moved to Engineering Management track, given opportunity to lead and manage CTG late in the year.
- Patent filings.
Personal:
“RPU” RISC-V soft CPU core able to run DooM on own SoC implementation to HDMI outut.
2021
- Part of the FidelityFX Super Resolution 1.0 team.
- Drove FidelityFX on Console project to adapt new technologies, including FSR.
- Management of FidelityFX on Console roadmap, strategy and customer engagement.
- “FidelityFX on Xbox” public announcement management.
- Hybrid Raytracing and FidelityFX presentations.
- Assisted with Amd.com, GPUopen.com technical marketing direction.
- Joined Core Technology Group within Game Engineering Organization.
2020
Senior Member of Technical Staff, Developer Technology Engineer, AMD
- Started “FidelityFX on Console” initiative.
- Performance Optimization and debug of new DirectX 12 Ultimate features on new GPU hardware.
- Authored GPUOpen tutorials.
- Created DirectX12 Ultimate video content.
- Promoted to SMTS
2019
Member of Technical Staff, Developer Technology Engineer, AMD
- Joined Game Engineering Organization within AMD
- Game-side Mesh Shader implementation and optimization.
- Game stability and optimization work.
Personal:
Own FPGA RISC-V CPU “RPU” Listed on official RISV-C core implementation list.
2018
- Solely responisble for driver optimization on most popular game title of the year.
- Optimization work on 3 other DirectX 12 and 11 titles.
- Created what would become the Unreal Engine 4 optimization patches on GPUOpen.
Personal:
Started work on my own RISC-V FPGA CPU, “RPU” - continued the “Designing a CPU in VHDL” blog series using this core.
2017
- Joined AMD in late 2016
- Optimized DX12 driver for 2 titles, gaining up to 20% performance gains over the optimization period.
- Optimized DX11 driver for 4 titles, gaining in excess of 35% performance gains on one.
- New hardware bringup optimization.
- Contributor to Vulkan KHR_shader_subgroup extension.
- Contributor to Vulkan 1.1
2016
Senior Director, Parallel and Graphics Debugger Systems, Codeplay Software
- Delivered Vulkan SDK Samples and Documentation for mobile IHV.
- Attended Khronos standards body meetings.
2015
Senior Director, Parallel and Graphics Debugger Systems, Codeplay Software
- Advised IHV on feasibility of proposed radical new Processor-in-memory (PIM) computation hardware in mobile for graphically intensive markets.
- Delivered proof-of-concept LLDB debugger for new PIM architecture.
- Developed RenderScript debugger based on LLDB.
- Speaker at GDC Khronos sessions on new SYCL standard for cross-platform, single-source asynchronous compute.
Personal:
Blog series “TeensyZ80” on running a Z80 CPU using a microcontroller emulating the main system board. Touched on hardware considerations, design speccing, low-level development and implemented OS features such as multithreadding.
Started personal blog series “TPU” on Designing a CPU in VHDL. Walks through the implementation of a 16-bit custom CPU named TPU, with associated peripherals such as UART. Featured on Hackaday.
2014
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Advised IHV of hardware features required for source level GPU shader debugging, including true jit-compiled on-target expression evaluation.
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Delivered source-level debugger based on LLDB for a mobile GPU.
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Oversaw delivery of source-level debugger based on LLDB for a DSP.
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Speaker at the San Francisco LLVM meeting, discussing bringing new architectures to the LLDB debugger project such as Qualcomms Hexagon DSP.
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Patent: Multi-processor code for modification for storage areas - “A method for processing computer program code to enable different parts of the computer program code to be executed by different processing elements of a plurality of communicating processing elements.”
Personal:
Blog series “Pi On the Wall” creating a wall-mounted home server with a modified Raspberry Pi board, custom power solution and enclosure. Featured on Hackaday.
2013
- Developed subset of Conformant OpenCL library functions using ARM NEON SIMD intrinsics and assembly.
- Delivered source-level debugger based on LLDB for a mobile GPU with no hardware debugging features to customer (Software Emulation).
- Developed Heterogeneous debugger for CPU and GPU based on LLDB on Android, with integration into IDE.
2012
- Developed and integrated LLVM optimizations for a ray-tracing shader compiler dealing with ray differential traversal.
- Internal project using Unreal Engine to utilize SPUs on PS3 more effectively and associated case study.
Launched own indie racing car game with bespoke online services system.
2011
2010
Technology Director - Games
2009
- Migrated entire renderer thread of AAA PS3 game engine to a single SPU.
- Optimized PSN game by offloading significant portions to SPU.
- Integrated technology into a AAA game engine for PlayStation3.
- Low level SPU optimization for software caching schemes and async DMA.
2008
Lead PS3 Developer
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Developed the Offload C++ system for migrating blocks of code in a single-source way to accellerators such as PS3 SPUs.
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Developed various optimizations for the Offload C++ system mainly encompassing memory and pointer alignment details being preserved through to the backend as far as possible for late optimization.
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Winner of the Elektra 2008 Research and Design award.
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Continued C backend work for multiple backend toolchain support, and extending level of C++ high level constructs able to be build via the C backend.
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Paper: Strict and Relaxed Sieving for Multi-Core Programming. MULTIPROG’08
2007
2006
Compiler Developer
- Joined Codeplay Software Ltd as a Compiler Developer.
- Developed Runtime for Sieve C++ speculative auto-parallelization systems.
- Graduated Glasgow University BScHons Software Engineering.
2005
- Summer Internship at Graham Technologies writing a network debugger with unit-test scripting capability which was subsequently integrated into main product line.
2004
- EPSRC Funded research project at Glasgow University looking at improving Computer Science skills in schools, with overall aims of increasing CompSci higher education graduates.
Before 2004
- Quake 3 mod scene member
- Assisted with many total conversions: Quake 3 Fortress, RTCW: WolfTactics, Enemy Territory Fortress
- Self Employed Web designer and system builder
- Developed multiple freeware tools - most popular was a system tray timer and notification aid for use with UK free, time based, dial up internet service providers.
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